PUBLIC RECORD VERSION
In the Matter of Rambus, Inc. Docket No. 9302
OPINION OF THE COMMISSION
By HARBOUR, Commissioner, for a unanimous Commission.
Table of Contents
I.          INTRODUCTION......................................................3
II.        BACKGROUND .......................................................5
A.         Technology Background ............................................5
1.         The Function of Computer Memory .............................5
2.         Evolution of RDRAM and SDRAM Memory Technologies:
Breaking Through the Memory Bottleneck........................6
3.         The Four Relevant Technology Markets..........................9
a.          Latency Technology....................................9
b.         Burst Length Technology...............................10
c.          Data Acceleration Technology...........................11
d.         Clock Synchronization Technology.......................11
B.         Procedural History................................................12
1.         History of FTC Matter.......................................12
a.          Pre-Trial Orders......................................13
b.         ALJ McGuire's Initial Decision..........................15
c.          Questions Raised on Appeal/Cross Appeal.................16
d.         Re-Opening of the Record Before the Commission ..........17
e.          Motion for Sanctions..................................17
2.         Non-FTC Judicial Developments Relating to this Proceeding ........17
III.       STANDARD OF REVIEW..............................................21
A. Standard of Proof: The Preponderance of the Evidence Standard Applies in
FTC Adjudications................................................21
1.         Relationship between Patent and Antitrust Law in Cases Involving Fraud on the Patent Office or Patent Enforcement Initiated in
Bad Faith .................................................22
2.          Standard of Proof Should Be Commensurate With Proposed Remedy . . 24
3.         Chilling Participation in SSOs.................................25
4.         Reliance on Testimony Rather than Contemporaneous
Written Evidence...........................................26
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IV.       MONOPOLIZATION CLAIM ..........................................27
A.        Exclusionary Conduct .............................................28
1.         Framework for Analysis......................................28
a.          Legal Circumstances ..................................30
b.         Factual Circumstances.................................32
c.          Nature of the Conduct .................................35
2.         Rambus's Course of Conduct..................................36
a.          The Chronology of Concealment.........................37
b.         Rambus's "Notice" to JEDEC...........................48
3.         The JEDEC Environment ....................................51
a.          EIA/JEDEC Policies and their Dissemination...............52
b.         Rambus's Understanding of JEDEC's Policies..............53
c.          Other JEDEC Participants' Understanding of JEDEC's
Policy Objectives.....................................54
d.         Disclosure Expectations of JEDEC Members...............55
e.          The Behavior of JEDEC Participants .....................57
f.          Knowledge of JEDEC Participants .......................59
4.         Rambus's Conduct Was Deceptive.............................66
5.         Rambus's Procompetitive Justification for its Conduct .............68
B.         Possession of Monopoly Power......................................72
C.         Causation.......................................................73
1.         Link between Rambus's Conduct and JEDEC's Standard-Setting Decisions .................................................74
2.         Link Between JEDEC's Standards and Rambus's Monopoly Power ... 77
3.         Rambus's Claims That The Chain of Causation Was Broken.........79
a.          Rambus's Intel Claim .................................79
b.         Rambus's Inevitability/Superiority Claim..................81
c.          Rambus's Claim that the Link between its Conduct and the Standards Did Not Matter ..............................96
d.         Rambus's "No Lock-In" Claim..........................98
4.         Rambus's Claim that its Acquisition of Monopoly Power
Did Not Matter............................................114
V.         SPOLIATION .......................................................115
VI.       CONCLUSION ......................................................118
VII.     REMEDY...........................................................119
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PUBLIC RECORD VERSION I. INTRODUCTION1
Rambus Inc. is a developer and licensor of computer memory technologies. For more than four years during the 1990s, Rambus participated as a member of the Joint Electron Device Engineering Council (JEDEC), an industrywide standard-setting organization (SSO) that operated on a cooperative basis. Through a course of deceptive conduct, Rambus exploited its participation in JEDEC to obtain patents that would cover technologies incorporated into now-ubiquitous JEDEC memory standards, without revealing its patent position to other JEDEC members. As a result, Rambus was able to distort the standard-setting process and engage in anticompetitive "hold up" of the computer memory industry. Conduct of this sort has grave implications for competition. The Federal Trade Commission (FTC or Commission) finds that Rambus's acts of deception constituted exclusionary conduct under Section 2 of the Sherman Act, and that Rambus unlawfully monopolized the markets for four technologies incorporated into the JEDEC standards in violation of Section 5 of the FTC Act.
Standard setting occurs in many industries and can be highly beneficial to consumers. Standards can facilitate interoperability among products supplied by different firms, which typically increases the chances of market acceptance, makes the products more valuable to consumers, and stimulates output. But standard setting also poses some risks of harm to competition. By its very nature, standard setting displaces the competitive process through which the purchasing decisions of customers determine which interoperable combinations of technologies and products will survive.
Typically, the procompetitive benefits of standard setting outweigh the loss of market competition. For this reason, antitrust enforcement has shown a high degree of acceptance of, and tolerance for, standard-setting activities. But when a firm engages in exclusionary conduct that subverts the standard-setting process and leads to the acquisition of monopoly power, the procompetitive benefits of standard setting cannot be fully realized.
This opinion uses the following abbreviations:
CA - Complaint Counsel's Appendix
CE - Order Granting Complaint Counsel's Motion for Collateral Estoppel
CCAB - Complaint Counsel's Appeal Brief
CCRB - Complaint Counsel's Reply Brief
CX - Complaint Counsel's Exhibit
DX - Demonstrative Exhibit
ID - Initial Decision of the Administrative Law Judge (ALJ)
IDF - Numbered Findings of Fact in the ALJ's Initial Opinion
JX - Joint Exhibits
RA - Respondent's Appendix
RB - Respondent's Brief on Appeal and Cross-Appeal
RFF - Respondent's Proposed Findings of Fact
RRB - Respondent's Rebuttal Brief
RX - Respondent's Exhibit
Tr. - Transcript of Trial before the ALJ.
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At the beginning of a standard-setting process, if there are a number of competing technologies, and if any one of them could win the standards battle, then no single technology will command more than a competitive price. Once the standard has been set, however, the dynamic changes. Soon after a standard is adopted, industry participants likely will start designing, testing, and producing goods that conform to the standard. Early in the process of implementing a standard, industry members still might find it relatively easy to abandon one technology in favor of another. But as time passes, and the industry commits greater levels of resources to developing products that comply with the standard, the costs of switching to alternative technologies begin to rise. Industry members may find themselves "locked in" to the standardized technology once switching costs become prohibitive. Once lock-in occurs, the owner of the standardized technology may be able to "hold up" the industry and charge supracompetitive rates.
Many SSOs have taken steps to mitigate the risk of hold-up by avoiding unknowing lock-in to a technology that may command supracompetitive rates. Many SSOs, for example, require their members to reveal any patents and/or patent applications that relate to the standard. These types of disclosures enable SSO members to evaluate potential standards with more complete information about the likely consequences, before the standard is finalized. Some SSOs also require members to commit to license their patented technologies on reasonable and nondiscriminatory (RAND) terms, which may further inform SSO members' analysis of the costs and benefits of standardizing patented technologies.
JEDEC operated on a cooperative basis and required that its members participate in good faith. According to JEDEC policy and practice, members were expected to reveal the existence of patents and patent applications that later might be enforced against those practicing the JEDEC standards. In addition, JEDEC members were obligated to offer assurances to license patented technologies on RAND terms, before members voted to adopt a standard that would incorporate those technologies. The intent of JEDEC policy and practice was to prevent anticompetitive hold-up.
Rambus, however, chose to disregard JEDEC's policy and practice, as well as the duty to act in good faith. Instead, Rambus deceived the other JEDEC members. Rambus capitalized on JEDEC's policy and practice - and also on the expectations of the JEDEC members - in several ways. Rambus refused to disclose the existence of its patents and applications, which deprived JEDEC members of critical information as they worked to evaluate potential standards. Rambus took additional actions that misled members to believe that Rambus was not seeking patents that would cover implementations of the standards under consideration by JEDEC. Rambus also went a step further: through its participation in JEDEC, Rambus gained information about the pending standard, and then amended its patent applications to ensure that subsequently-issued patents would cover the ultimate standard. Through its successful strategy, Rambus was able to conceal its patents and patent applications until after the standards were adopted and the market
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was locked in. Only then did Rambus reveal its patents - through patent infringement lawsuits against JEDEC members who practiced the standard.2
The Commission finds that Rambus violated Section 5 of the FTC Act by engaging in exclusionary conduct that contributed significantly to the acquisition of monopoly power in four relevant and related markets. We further find a sufficient causal link between Rambus's exclusionary conduct and JEDEC's adoption of the SDRAM and DDR-SDRAM standards (but not the subsequent DDR2-SDRAM standard). Questions remain, however, regarding how the Commission can best determine the appropriate remedy. Accordingly, the Commission orders additional briefing for further consideration of remedial issues.
II. BACKGROUND
A. Technology Background
The dispute before us involves four relevant product markets: (1) latency technology; (2) burst length technology; (3) data acceleration technology; and (4) clock synchronization technology. These markets include technologies that, beginning in 1993, have been incorporated into the JEDEC standards for computer memory, and over which Rambus now claims patent rights.3
1. The Function of Computer Memory
Main memory - often referred to as random access memory, or RAM - consists of integrated circuits that hold temporary instructions and data for the central processing unit (CPU), the central "brain" of a computer system.4 The CPU performs each command given by a computer user by extracting instructions from the computer's memory, then decoding and
Complaint Counsel also allege that Rambus engaged in spoliation of evidence. Rambus instituted a document retention policy that entailed the systematic destruction of a large volume of documents. This destruction policy included documents related to Rambus's participation in JEDEC and Rambus's patent prosecution files. As discussed in greater detail infra, Section V, however, we need not resolve the spoliation question because our findings are firmly grounded on the surviving evidence.
Rambus has not contested the definition of the four relevant product markets delineated by Complaint Counsel. See infra note 394. Nor does Rambus contest Complaint Counsel's allegation, or the ALJ's finding (which we adopt), that the relevant geographic market is worldwide. Complaint *\ 117; IDF 1016-17; ID 250.
4
Rhoden, Tr. 271-72; RA 3. Most types of RAM are volatile, which means they lose all data when the
power is turned off or the system shuts down. CA A-3; RA 3.
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executing them. Most computers use a type of RAM known as dynamic random access memory (DRAM),5 which stores and processes information while the computer is on.6
DRAM is only one piece in the computer hardware infrastructure. A typical personal computer is built around a motherboard - the main circuit board upon which many of the important components of a computer system are fastened. The motherboard includes, for example, the CPU, chipset, and graphics and sound cards. A computer system also includes a system clock, a power supply, mass storage devices (such as hard drives or CD ROM drives), assorted controllers that enable the computer to connect to external peripheral devices (such as monitors, printers, and scanners), and a main memory system (containing DRAM). The main memory circuits typically attach to the memory module (a small printed circuit board that plugs into the motherboard).7 Communications between the main memory circuits and the CPU are managed by a memory controller, which generally is part of the chipset.8 DRAM must be compatible and interoperable with other components in the same computer system.9
2. Evolution of RDRAM and SDRAM Memory Technologies: Breaking Through the Memory Bottleneck
In the early 1980s, an imbalance emerged in the speed at which CPU technology was developing relative to memory technology.10 CPU speeds have doubled every eighteen months for the past two decades,11 while memory speeds have increased more slowly. This "memory
DRAM is "dynamic" because it must be refreshed every fraction of a second to prevent memory loss. Rhoden, Tr. 266-67.
Rhoden, Tr. 267-68. DRAM also is incorporated into other electronic devices such as servers, printers, and cameras. IDF 3; Rhoden, Tr. 298; RA 3.
7   Rhoden, Tr. 269, 272-73; RA 4.
8   Rhoden, Tr. 275-76; CA A-1; RA 2.
9   See, e.g., IDF 6.
10   IDF 27-40.
Farmwald, Tr. 8068 (describing "Moore's law," based on observations by Intel co-founder Gordon Moore regarding the rate of increase in CPU speeds).
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bottleneck problem"12 became a widely recognized concern in the computer hardware industry during the early 1990s.13 The industry considered several different solutions.14
One of those solutions - Rambus DRAM, or RDRAM - was developed by Rambus.15 Rambus was founded in March 1990 by two professors who wanted to commercialize their concept for a new DRAM design that would break the "memory bottleneck."16 Rambus develops, secures patents on, and licenses technologies to companies that manufacture semiconductor memory devices. Rambus is not a manufacturing company; rather, Rambus earns its revenue through the licensing of its patents.17
A month after its founding, on April 18, 1990, Rambus filed Patent Application No. 07/510,898 (the '898 application) with the U.S. Patent Trademark Office (PTO).18 This application described many of the technologies developed and integrated into the initial RDRAM design. The '898 application also is the original source of the patents that Rambus has asserted with regard to the four technologies at issue in this case. The PTO issued a restriction requirement in late 1990, requiring Rambus to decide which of the multiple claimed inventions it wished to pursue in the '898 application. On March 5, 1992, Rambus responded to the PTO's demand by filing ten divisional applications.19
One of Rambus's founders, Paul Michael Farmwald, testified that the "memory bottleneck" problem was a potential bottleneck in which memory chip performance could limit computer performance. Farmwald, Tr. 8068-69, 8071-73.
13   IDF 36-40.
14  See, e.g., CX 711 at 1; Sussman, Tr. 1359-60, 1364; G. Kelley, Tr. 2584-85. In the last decade most DRAMs have been synchronized with the system clock, in order to maximize the number of instructions a CPU can process in a given time. This design is called "synchronous DRAM," or SDRAM (as distinguished from earlier, asynchronous DRAMs). Jacob, 5394-95; CA A-4; RA 5.
RDRAM reflected innovations with respect to bus width, the interface between the bus and computer chips, and the DRAM. IDF 86-90; CA A-4; RX 81 at 3,7; Horowitz, Tr. 8618-20; Rhoden, Tr. 400-401. Buses essentially are a computer's highway system. A memory bus comprises the lines that connect each memory device to the memory controller. Computer buses, like highways, can vary by width, which means they can have a differing number of lines linking the computer's components (just as highways may have more or fewer lanes to carry traffic). The speed at which a computer operates is affected by its buses. Rhoden, Tr. 275-76; CA A-1.
16   IDF 27-48, 58; CX 533 at 8; CX 545 at 7; Farmwald, Tr. 8089-93; Horowitz, Tr. 8486.
17   Parties' First Set of Stipulations, Item 2 (April 23, 2003); see also CX 2106 (Farmwald FTC Dep.) at 220 (in camera) ("[r]oyalties are the lifeblood of Rambus").
18   CX 1451.
19
A restriction requirement forces a patent applicant to separate each distinct invention or group of
inventions into separate applications known as "divisionals." Nusbaum, Tr. 1509-11.
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Beginning in 1990, Rambus tried to license its RDRAM technology to manufacturers of DRAM chips and DRAM-compatible microprocessors.20 Rambus attempted to position RDRAM as the de facto standard.21 Rambus made numerous presentations on RDRAM to the major DRAM manufacturers in an effort to persuade them to adopt the technology.22 Rambus also tried to develop relationships with major systems companies, and pursued commitments from these companies to introduce systems using RDRAM technology.23 RDRAM failed to achieve significant market success, however, at least in part because manufacturers were reluctant to pay royalties and licensing fees to Rambus.24
These manufacturers rejected RDRAM and instead turned to standards promulgated by JEDEC. JEDEC was a semiconductor engineering standardization body within the Electronic Industries Association (EIA). It comprised manufacturers and purchasers of DRAM, as well as producers of complementary products and computer systems.25 JEDEC's JC 42.3 committee was responsible for RAM issues, and, in particular, for the development of DRAM standards.26
See CX 533 at 9-10. Major DRAM manufacturers included Samsung Electronics Co., Micron
Technology, Inc., Hyundai Electronics Industries (subsequently, Hynix Semiconductor Inc.), LG Semicon Ltd., NEC Corporation, Siemens AG (subsequently, Infineon Technologies AG), Toshiba, Mitsubishi Electric Corporation, and Hitachi, Ltd. See CX 2747 at 7.
21    Id. at 3.
22   See, e.g., Sussman, Tr. 1429-31; CX 535 at 1, 4-5; CX 543a at 11; CX 2107 at 63 (Oh FTC Dep.) (in camera).
23   See, e.g., Kellogg, Tr. 5049-54; Bechtelsheim, Tr. 5816-19; CX 535 at 2, 5-6.
See, e.g., Rapp, Tr. 10248-49 (RDRAM sales represented less than 2% of the market for at least six years following the adoption of SDRAM) (providing market-share statistics); JX 36 at 7 ("Some Committee members did not feel that the Rambus patent license fee fit the JEDEC requirement of being reasonable."); CX 961 at 1 (September 1997 Intel e-mail to Rambus Chief Executive Officer (CEO) Geoff Tate, stating that, upon analyzing the royalty obligations attached to RDRAM, the industry would develop alternatives); RX 1482 at 12 (post-1996 Rambus Strategic Review stating, "Memory manufacturers need to focus on cost reduction to restore profitability" and describing RDRAM as "a guaranteed bad bet for margin enhancement").
25   See J. Kelly, Tr. 1774-75; Rhoden, Tr. 293-94; Landgraf, Tr. 1685; JX 18 at 1-3. Between 1991 and 1996, JEDEC was an organization within the EIA. IDF 222; J. Kelly, Tr. 2075. EIA engages in a variety of different activities in support of the electronics industry in the United States, including government relations, marketing research, trade shows, and standard setting. J. Kelly, Tr. 1750-51, 1764. In 1998, EIA was renamed the Electronic Industries Alliance, and JEDEC became an EIA division. CX 302 at 11. By the first quarter of 2000, JEDEC became separately incorporated, but remained contractually affiliated with EIA. J. Kelly, Tr. 1752; CX 302 at 11.
26    Rhoden, Tr. 284-85, 288; Williams, Tr. 763; J. Kelly, Tr. 1769. JEDEC was divided into several committees. Each committee focused on a particular aspect of the semiconductor and solid state electronics industries, and was subdivided into several subcommittees.
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At issue here are three generations of DRAM standards developed and adopted by JEDEC: synchronous DRAM (SDRAM),27 DDR SDRAM,28 and DDR2 SDRAM.29 In the course of designing these standards and determining which technologies would be incorporated, the JEDEC members evaluated numerous technologies relating to various aspects of main memory, including the technologies that comprise the four relevant product markets in this case. Rambus eventually claimed that its patents cover the specific versions of these four technologies that ultimately were adopted by JEDEC for the SDRAM, DDR SDRAM, and DDR2 SDRAM standards.
3. The Four Relevant Technology Markets a. Latency Technology
Latency is a measure of the amount of time between a request and a response.30 Memory latency is the length of time between the memory's receipt of a read request and its release of data corresponding with the request.31 Latency technology comprises those technologies used to control the length of this time period.32
In the early 1990s, several types of latency technology were available, including programmable latency, fixed latency, blowing a fuse on a DRAM, and dedicated pins. These
27 JEDEC designed the SDRAM standard during the early 1990s and first published it in 1993. IDF 297-315, 355-56. By 1998, JEDEC-compliant SDRAM was the most widely used type of memory device. IDF 370; CA A-5. The SDRAM standard incorporated technologies from the latency and burst length markets. IDF 355; 1013; RA 5. Rambus has asserted that its patents cover the implementations of these two technologies in the SDRAM standard. IDF 1022-29.
DDR SDRAM was a second-generation standard promulgated by JEDEC. RA 2. DDR SDRAM included some of the features of SDRAM, and also incorporated new technologies that increased the speed and efficiency of the memory system. IDF 430; CA A-1. JEDEC first published DDR SDRAM in 1999. IDF 427-29; RA 2. JEDEC-compliant DDR SDRAM was forecast to overtake SDRAM as the predominant memory device by 2002-03. See McAfee, Tr. 7227 (presenting DX 141), 7430-31 (presenting DX 219). DDR SDRAM incorporated technologies from the latency, burst length, data acceleration, and clock synchronization markets. Rambus has asserted that its patents cover the implementations of these four technologies in the DDR SDRAM standard. IDF 1022-29.
29
DDR2 SDRAM is the third-generation standard that JEDEC developed using SDRAM technology. RA 2; CA A-1. By the time of the 2003 trial, JEDEC had published to its members preliminary specifications for this standard that retained the latency, burst length, data acceleration, and clock synchronization technologies that Rambus has claimed infringe its patents. RA 2.
30    IDF 114.
31    Horowitz, Tr. 8529-30.
32   McAfee, Tr. 7348.
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alternative solutions are discussed in greater detail below.33 JEDEC first incorporated programmable column address strobe (CAS) latency into its SDRAM standard and retained the technology in its DDR SDRAM and DDR2 SDRAM standards.34 Programmable CAS latency controls data output timing by determining the number of clock cycles that should be allowed to elapse after a defined point.35 Programmable CAS latency provides users of DRAMs with flexibility, i.e., a single part can be programmed so as to provide the optimal latency in a variety of systems.36
Rambus claims that its patents cover JEDEC's implementation of programmable CAS latency technology.
b. Burst Length Technology
Burst length technology controls the amount of data transferred between the CPU and memory in each transmission. JEDEC's SDRAM, DDR SDRAM, and DDR2 SDRAM standards adopted programmable burst length technology, which provides a means for varying the number of cycles of data that are transmitted to the memory controller in response to an individual command.37 Programmable burst length technology is similar to programmable CAS latency technology in that it allows DRAM customers to use one part for many different types of machines that require different burst lengths.38
In the early 1990s several alternatives to programmable burst length were available, as discussed in greater detail below.39 One alternative was the use of fixed burst length parts.40 Another alternative was to use "burst terminate commands," which establish a long burst length
See infra Section IV.C.3.b.
34   IDF 355, 433; RA 2, 5.
35    CA A-3.
36    Soderman, Tr. 9346-47, 9433-34; Kellogg, Tr. 5140.
37   CA A-3.
TO
See, e.g., G. Kelley, Tr. 2550-51 ("The programmable [burst length] feature allowing you to make that selection when the PC or computer powered up was a nice feature because it allowed you to use devices that were common from multiple suppliers, put them into many different types of machines. . . . One part number fits many applications.").
39
See infra Section IV.C.3.b.
40 Jacob, Tr. 5398-99.
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as the default and use the memory controller to terminate the burst if a shorter burst length is desired.41
Rambus claims that its patents cover JEDEC's implementation of programmable burst length technology.
c. Data Acceleration Technology
Data acceleration technology determines the speed at which data are transmitted between the CPU and memory. JEDEC's DDR SDRAM and DDR2 SDRAM standards adopted one particular type of data acceleration technology, known as dual-edge clocking, which captures data off both the rising and falling edges (the "tick" and the "tock") of the clock.42 This technology enables twice the amount of data to be sent in each clock cycle compared to single-edge clocking, by which data are sent only on one edge of the clock.43
When JEDEC was considering whether to adopt dual-edge clocking technology as part of its DDR SDRAM standard, several alternatives were available. As discussed in greater detail below,44 alternative technologies included interleaving ranks on the module (using different clock signals for separate groups of DRAM chips), double clock frequency (operating a single-edge clock at twice the frequency of a dual-edge clock45), and toggle mode (which, as formulated by IBM, combined synchronous and asynchronous features46).
Rambus claims that its patents cover JEDEC's implementation of dual-edge clocking technology.
d. Clock Synchronization Technology
Clock synchronization technologies coordinate the internal clock on each DRAM chip with the timing of the computer's system clock. Phase lock loop (PLL) and delay lock loop (DLL) technologies use circuits to align more closely the timing of the internal clock on each
41
Jacob, Tr
. 5409-10.
42
RA 3.
43
CA A-2.
44
See infra
Section IV.C.3.b.
45
Jacob, Tr
. 5433-34.
46 See Jacob, Tr. 5608, 5416-17; Soderman, Tr. 9398; G. Kelley, Tr. 2514.
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DRAM with the system clock.47 Rambus developed a technology that places a PLL/DLL48 on the SDRAM chip itself.49 On-chip PLL/DLL clock synchronization technology was incorporated into JEDEC's DDR SDRAM and DDR2 SDRAM standards.
One alternative approach to on-chip PLL/DLL involved placing a PLL/DLL circuit on the memory controller that synchronizes all DRAMs.50 Another approach involved placing one or more PLL/DLL circuits on the memory module.51 Still other alternatives involved the use of vernier circuits, which introduce static delays on a signal to reduce timing uncertainties in a memory system, or reliance on a data strobe to signal the memory controller the timing of data capture.52 These alternatives, which were considered by JEDEC prior to its adoption of on-chip PLL/DLL, are discussed in greater detail below.53
Rambus claims that its patents cover JEDEC's implementation of on-chip PLL/DLL technology.
B. Procedural History
1. History of FTC Matter
The Complaint in this matter was issued on June 18, 2002. The Complaint charged that Rambus: (1) monopolized certain memory technology markets through a pattern of anticompetitive and exclusionary conduct; (2) attempted to monopolize these markets; and (3) engaged in unfair methods of competition.54
47 Jacob, Tr. 5442-43; Kellogg, Tr. 5150-55; RA 4; CA A-3. PLLs use voltage oscillators to synchronize the internal clock with the system clock. See Jacob, Tr. 5443, 5616-17; Soderman, Tr. 9401. In contrast, DLLs introduce a variable amount of delay into the internal clock to synchronize that clock with the system clock. See Jacob, Tr. 5443, 5616-17; Soderman, Tr. 9401.
Horowitz, Tr. 8607 (Rambus co-founder testified that, under his usage of the terms, "a PLL is the generic term for any circuitry that adjusts phase, so a DLL is a kind of PLL").
49    Farmwald, Tr. 8117-18; Horowitz, Tr. 8503-05; 8521-22, 8527-28.
50    Jacob, Tr. 5445.
51    Jacob, Tr. 5448-49.
52    Jacob, Tr. 5450, 5456-57.
53   See infra Section IV.C.3.b.
54   See Complaint 1111 122-24.
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The Complaint's allegations focused on Rambus's participation in JEDEC. It alleged that Rambus deceived JEDEC's members by, for example, concealing the fact that it
was actively working to develop, and did in fact possess, a patent and several pending patent applications that involved specific technologies proposed for and ultimately adopted in the relevant standards. By concealing this information - in violation of JEDEC's own operating rules and procedures - and through other bad-faith, deceptive conduct,
Rambus allegedly conveyed the "materially false and misleading impression that it possessed no relevant intellectual property rights"55 and that it had no plans to enforce any intellectual property rights that might later become relevant, leaving a materially misleading impression of its intellectual property ownership and plans.56 The Complaint further alleged that Rambus's conduct resulted in anticompetitive effects including: increased royalties; increased prices for memory products compliant with JEDEC standards; decreased incentives to produce memory using JEDEC-compliant memory technology; and decreased incentives to participate in, and rely on, standard-setting organizations and activities.57 According to the Complaint, Rambus gave no notice that it intended to claim patent rights over technologies used in JEDEC's DRAM standards, and, by failing to do so, likely affected the content of those standards and/or the terms on which Rambus later licensed its patent rights.58
a. Pre-Trial Orders
The case was first assigned to Administrative Law Judge (ALJ) James P. Timony and, upon his retirement, was reassigned to Chief ALJ Stephen J. McGuire.59 Before retiring, ALJ Timony issued two orders on February 26, 2003: first, an Order Granting Complaint Counsel's Motion for Collateral Estoppel; and second, an Order on Complaint Counsel's Motions for Default Judgment and for Oral Argument. Both orders influenced the trial and ALJ McGuire's Initial Decision.
See Complaint *\ 2; see also id. ^[ 54 (alleging deception and bad-faith conduct), 71 (alleging that Rambus conveyed "a materially false and misleading impression").
56   See Complaint ffl| 70-78.
57   See Complaint ffl| 119-120.
58   See Complaint ffl| 62,65,69,70-78,86.
59
All references within this opinion to "the ALJ," unless otherwise specifically identified, will refer to ALJ
McGuire.
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On February 12, 2003, Complaint Counsel filed a motion seeking recognition of the collateral estoppel effect of prior factual findings that Rambus had destroyed material evidence. ALJ Timony granted the motion, thus barring Rambus from re-litigating certain findings of fact made by the district court in prior private litigation, Rambus Inc. v. Infineon Technologies AG.60 Those findings included:
1.         When Rambus instituted its document retention policy in 1998, it did so, in part, for the purpose of getting rid of documents that might be harmful in litigation.
2.         Rambus, at the time it implemented its document retention policy, ... [c]learly ... contemplated that it might be bringing patent infringement suits during this timeframe if its efforts to persuade semi-conductor manufacturers to license its JEDEC-related patents were not successful.
3.         Rambus's document destruction was done in anticipation of litigation.61
Complaint Counsel also moved for default judgment as a remedy to counter Rambus's intentional destruction of documents. ALJ Timony denied the motion, but set forth seven rebuttable adverse presumptions against Rambus. The presumptions included:
1.         Rambus knew or should have known from its pre-1996 participation in JEDEC that developing JEDEC standards would require the use of patents held or applied for by Rambus;
2.         Rambus never disclosed to other JEDEC participants the existence of these patents; [and]
3.         Rambus knew that its failure to disclose the existence of these patents to other JEDEC participants could serve to equitably estop Rambus from enforcing its patents as to other JEDEC participants.62